1. Field of the Invention
The present invention relates to semiconductor devices and particularly to a semiconductor device including a holding circuit which operates according to signals asynchronous with respect to each other.
2. Description of Related Art
A logic circuit which operates according to a plurality of signals that are asynchronous with respect to each other cannot ensure meeting the specification of a setup time or a hold time of the logic circuit in relation to the signals relative to each other. Thus, the logic circuit which operates according to asynchronous signals inevitably enters a metastable state where an output value is indeterminate.
The metastable state is described hereinafter with reference to a latch circuit as an example. FIG. 3 is a circuit diagram of a latch circuit 11. The latch circuit 11 may be a circuit to store the operational state of a memory cell in a DRAM, for example. Specifically, the latch circuit 11 stores either the refresh state or the read/write state according to an input signal. A processor 12 controls the operational state of a memory cell according to the output of the latch circuit 11.
The latch circuit 11 includes a set terminal S, a reset terminal R, and an output terminal Q. FIG. 4 is a timing chart of the operation of the latch circuit 11. As shown in FIG. 4, after a High-level Refresh signal is input to the reset terminal R, the latch circuit 11 holds the refresh state until a Low-level R/W signal is input to the set terminal R. On the other hand, after a Low-level R/W signal is input to the set terminal R, the latch circuit 11 holds the read/write state until a High-level Refresh signal is input to the reset terminal R.
If the changing R/W and Refresh signals relative to each other cannot meet the specification of a setup time or a hold time, the values held in the holding section 13 may not be fixed to either High level or Low level. This occurs, for example, when the signals are input at the same time to the set terminal S and the reset terminal R and as a result the value held by the holding section 13 is stabilized at an intermediate voltage (i.e. the timings t3 to t5 in FIG. 4).
The state where the latch circuit 11 holds an intermediate voltage such that an indeterminate state is transferred to a circuit in the subsequent stage is called a metastable state (i.e. the timings t5 to t6 in FIG. 4). Although the metastable state shifts to a High-level or Low-level state after a certain time period, the length of the period is unpredictable. Metastable states occur inevitably in a circuit to determine a value to hold according to signals that are asynchronous with respect to each other.
Various methods have been proposed to prevent metastable states. One exemplary method predicts the time when an output becomes unstable and adds a delay to the clock input to a processor connected with a circuit where a metastable state can occur. This method uses the fact that a period when a circuit output is unstable due to metastable is only temporary. Another exemplary method prevents metastable based on the majority decision of a plurality of latch circuits as disclosed in Japanese Unexamined Patent Publication No. 2000-261310 (referred to hereinafter as the related art 1).
FIG. 5 shows a logic LSI 100 according to the related art 1. The logic LSI 100 is a semiconductor device that operates in synchronization with a system clock SCK and receives an input signal AsyncIn that changes asynchronous with respect to the system clock SCK. Metastable states can thereby occur in the logic LSI 100.
As a measure to metastable states, the logic LSI 100 includes delay circuits 101a to 101n respectively having different delay times and flip-flops 102a to 102n to store asynchronous signals AsyncIn in synchronization with system clocks SCK. The flip-flops 102a to 102n are respectively connected with the corresponding delay circuits 101a to 101n. Asynchronous signals AsyncIn are input to the flip-flops 102a to 102n through the corresponding delay circuits 101a to 101n. Therefore, the asynchronous signals AsyncIn which are input to the flip-flops 102a to 102n delay by the connected delay circuits, so that the asynchronous signal AsyncIn and the system clock SCK which are input to each flip-flop have different timings from each other.
The outputs of the flip-flops 102a to 102n are input to a comparator 103. The comparator 103 selects a majority logic value among the outputs of the flip-flops 102a to 102n based on majority rule and outputs the majority logic value. A processor 104 operates according to the output of the comparator 103.
In the logic LSI 100 of the related art 1, input signals with different delay times are latched by a plurality of flip-flips, and a logic value is determined by majority rule. Thus, even when a metastable state occurs in some flip-flop, an error associated with the metastable state is not transmitted to the processor 104 because a majority logic value is determined by majority rule using the output values of the other flip-flops.
However, the logic LSI 100 of the related art 1 needs to include a plurality of delay circuits, a plurality of flip-flops, and a comparator, which causes an increase in circuit size. Further, a delay time until a signal is transmitted to a processor increases due to the delay circuits. A longer delay time until a signal is transmitted to a processor causes a longer time required to start executing the operation in response to an input signal. Accordingly, if a time period from the input of a signal to the end of the operation corresponding to the input signal is specified, it is sometimes unable to meet the specification. For example, a time period from the input of a read command to the output of data is specified for memories, and a too long internal signal delay time causes a failure to meet the specification on the time period from the command input to the data output.